1. Field of the Invention
The present invention relates to a delay-locked loop circuit, and more particularly, to the delay-locked loop circuit having wide frequency locking range and error-locking-avoiding function.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional delay-locked loop (DLL) circuit 100. The DLL circuit 100 comprises a phase/frequency detector 110, a current controller 120, a capacitor C1, a voltage control delay line (VCDL) 130, and a predetermined dummy delay 140.
Please continue referring to FIG. 1. The phase/frequency detector 110 comprises two input terminals for receiving a reference periodic signal CLKREF and a feedback periodic signal CKLFB respectively. The phase/frequency detector 110 determines the phase difference between the reference periodic signal CLKREF and the feedback periodic signal CKLFB and accordingly outputs the control signals SUP or SDN. For the example, when the phase of the reference periodic signal CLKREF is ahead of the phase of the feedback periodic signal CKLFB, the phase/frequency detector 110 outputs the control signal SUP; otherwise, when the phase of the reference periodic signal CLKREF falls behind the phase of the feedback periodic signal CKLFB, the phase/frequency detector 110 outputs the control signal SDN.
Please continue referring to FIG. 1. The current controller 120 is coupled to the output terminal of the phase/frequency detector 110 for receiving the control signals SUP or SDN. When the current controller 120 receives the control signal SUP, the current controller 120 sources current IX with the predetermined magnitude (not shown) to capacitor C1 for increasing the voltage VX; when the current controller 120 receives the control signal SDN, the current controller 120 sinks the current IX with the predetermined magnitude to the capacitor C1 for decreasing the voltage VX. The capacitor C1 is coupled between the output terminal of the current controller 120 and a ground terminal.
Please continue referring to FIG. 1. The VCDL 130 comprises two input terminals. One input terminal of the VCDL 130 is utilized for receiving the reference periodic signal CLKREF, and the other input terminal of the VCDL 130 is coupled to the capacitor C1 for receiving the voltage VX. The VCDL 130 delays the reference periodic signal CLKREF by a corresponding period of time DX (not shown) according to the voltage VX, and the delayed reference periodic signal CLKREF is outputted as a delayed periodic signal CLKOUT.
Please continue referring to FIG. 1. The predetermined dummy delay 140 is coupled between the output terminal of the VCDL 130 and the input terminal of the phase/frequency detector 110. The predetermined dummy delay 140 further delays the received delayed periodic signal CLKOUT by a predetermined period of time DP in order to generate the feedback periodic signal CLKFB, and then the generated feedback periodic signal CLKFB is fed to the phase/frequency detector 110.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating relationship between the reference periodic signal CLKREF and the delay periodic signal CLKFB. As shown in FIG. 2, by using the conventional DLL circuit 100, the phase of the delay periodic signal CKLOUT is set to prior to the phase of the reference periodic signal CLKREF by the predetermined phase PD (similar to the above-mentioned predetermined period of time DP).
Please refer to FIG. 3. FIG. 3 is a diagram illustrating the relationship between the voltage of the VCDL 130 and the delay time. The VCDL 130 controls the delay analogically. When a user needs to prolong the delay DX, the user can just increase the input voltage VX of the VCDL 130. As shown in FIG. 3, the axis of the voltage can be divided into three sections: section A, section B, and section C, in which the gradient is increasing gradually from the section A to section C. In other words, in section A, the variation of the voltage VX has minor effect to the delay DX. On the contrary, the delay DX varies enormously even when voltage VX is just slightly changed in section C. Therefore, when the required delay DX falls within the range of section C, the stability of the voltage VX becomes very critical. This is because the slightly variation of the voltage VX may greatly change the delay DX and to consequently result a huge error. Accordingly, the conventional DLL circuit 100 limits options for the reference periodic signal CLKREF and the delay phase, which is greatly inconvenient for the user.